The present invention relates to a semiconductor device having an MIS type structure, and, more specifically, to a nonvolatile semiconductor memory device and a method of manufacture thereof.
Nonvolatile semiconductor memory devices are usually formed as semiconductor integrated circuit devices. A typical example of such a device is a flash memory device that can be electrically written and erased. The flash memory device is described, for example, in Japanese Patent Laid-Open No. 276878/1987 and 219496/1991 and a paper by Kume, entitled xe2x80x9cA 1.28 xcexcm2 Contactless Memory Cell Technology for a 3V-Only 64 Mbit EEPROM,xe2x80x9d IEDM, 1992, 92-991 to 92-993.
FIG. 10 shows a cross-sectional structure of a main portion of a proposed (comparative) flash memory device. The main part of the memory often employs a so-called stack structure. The stack structure generally refers to a structure in which a capacitor for memory is formed over an electric switch circuit. In FIG. 10, reference number 601 represents a single crystal silicon substrate, 602 a device isolation oxide film, 603 a gate oxide film (tunnel insulating film), 606 a floating gate electrode, 607 an inter-layer insulating film, 608 a control gate electrode, 610 a source, 611 a drain, 609, 612 and 613 insulating films, 614 a source interconnect, and 615 a drain interconnect.
The construction of the main part of this memory will be described in detail. The gate oxide film 603 uses a silicon oxide film about 7.5-10 nm thick, which is generally formed by thermally oxidizing a silicon substrate. The floating gate electrode 606 is made of a polycrystalline silicon film doped with a high concentration of phosphorus and has a thickness of about 50 to 200 nm. The inter-layer insulating film 607 uses a laminated film 607 of SiO2 film/Si3N4 film/SiO2 film formed by low pressure chemical vapor deposition (LP-CVD). This laminated film 607 (of SiO2 film/Si3N4 film/SiO2 film) is generally called an ONO film (This abbreviation xe2x80x9cONO filmxe2x80x9d will be used hereinafter).
A first state of information in this flash memory-for example, writing of information-is accomplished as follows.
The drain 611 is set to a positive bias (for example +4V), the control gate electrode 608 is set to a negative bias (for example xe2x88x9210V), the source 610 is open, and the silicon substrate 601 is set to 0V. In this state, electrons stored in the floating gate electrode 606 are pulled out toward the drain 611 side, thus writing information. These voltages are each applied by using pulses about 100 microseconds long. With this method the electrons in the floating gate electrode 606 are pulled out toward the drain 611 by a Fowler-Nordheim tunneling current (hereinafter abbreviated F-N current).
A second state of information, for example, erasing of information, is done as follows. The control gate electrode 608 is set to a positive bias (for instance +10V), the silicon substrate 601 is set to a negative bias (for instance xe2x88x924V), and the source 610 and the drain 611 are set to an open state. In this state, electrons are injected into the floating gate electrode 606 from the silicon substrate 601, erasing the information. These voltages are applied by using pulses about 100 microseconds long.
While the holding of information in the first state is referred to as writing and that in the second state is referred to as erasing, these states of electric charge may be called in an opposite way. Naming of these states depends on how the electric charge operates. Whatever they are called, the same states have the same problem. In the following description, the writing and erasing refer to the states of charge as described above for the purpose of facilitating the understanding of explanation. It should be noted that the description of this invention also applies to the case of a it charge operation where the states of charge are called in a way opposite to this specification, by reading each of the charge states in this specification to mean the same but oppositely called state.
UK patent application No. 2,254,960 discloses an MOS device having reduced susceptibility to oxide degradation at high integration levels, the device having an improved breakdown voltage by preventing reaction between the gate oxide material and doped impurity used to improve the electrical conductivity of the gate. The gate, made of polycrystalline silicon, includes an upper polycrystalline silicon layer and a lower polycrystalline silicon layer, the lower layer having a larger grain size than the upper layer. The gate can be formed by initially forming an amorphous (lower) silicon layer and a polycrystalline silicon layer thereon, doping an impurity into the polycrystalline silicon layer and converting the amorphous silicon layer to a polycrystalline silicon layer, to form the layers having the necessary grain sizes. Illustratively, the amorphous silicon layer, converted to polycrystalline silicon, has a thickness of 20-100 nm.
Problems to Be Solved by the Invention
Writing and erasing of information in a flash memory is performed by injecting electrons into and pulling them out of the floating gate through the gate insulating film. The write/erase time or programming time depends on the Fowler-Nordheim tunneling current (F-N current) that flows in the gate insulating film. Because the F-N current depends largely on the thickness of the gate insulating film, the write/erase time decreases as the gate insulating film becomes thin. A reduction in thickness of the gate insulating film, however, induces the following problem, which is briefly explained by referring to the drawings.
FIG. 15 shows an electric field-current characteristic of an MOS capacitor before and after having constant current (F-N current) stresses applied thereto. The application of stresses means a test method for acceleratedly simulating stresses that would occur in the actual mounted state. That is, this method involves injecting a predetermined amount of charge into a memory cell and comparing the memory characteristics before and after the charge injection. The charge injection in this case is called stress application.
In FIG. 15, the solid line A represents a characteristic before the stress application and the dotted line B represents a characteristic after the stress application. In this example, an injection current density is 0.1 A/cm2 and an injected charge density is 1 C/cm2. As shown in FIG. 15, the leakage current of the MOS capacitor after stress application increases in a low electric field region (for example, below xc2x18 MV/cm). This is explained as follows. When the F-N current is injected into the gate insulating film for the application of stresses, holes injected into the gate insulating film form a new level in the gate insulating film and the leakage current through this level increases.
The leakage current in the low electric field region is the major cause for deterioration of the charge retention characteristics of flash memories. That is, the concrete causes of degraded charge retention characteristics include what are generally called a retention failure of flash memory (leakage of charge from the floating gate to the substrate side) and a disturbance failure (leakage from the substrate side to the floating gate side).
FIG. 16 shows the relation between the thickness of a gate insulating film and the current density in a flash memory cell. The characteristic given by black dots represents the relation between the thickness of a gate insulating film and the F-N current, and the characteristic given by blank dots represents the relation between the thickness of a gate insulating film and the leakage current at a low electric field. As can be seen from FIG. 16, the leakage current at the low electric field can be controlled by increasing the thickness of the gate insulating film. The leakage current at the low electric field and the F-N current are, however, in a trade-off relationship with respect to the thickness of the gate insulating film. Increasing the thickness of the gate insulating film therefore reduces the F-N current, giving rise to a new problem of increased programming (write/erase) time.
As a means to solve this problem, a method is proposed that introduces a trace amount of nitrogen into the conventional thermally oxidized film to suppress the leakage current at a low electric field. One such example is described in IEEE Electron Device Letters, Vol. 12, No. 11, p587, Nov. 1991. Even with this method, a sufficient level to ensure a desirable charge retention characteristic has not been reached.
An object of this invention is to provide a semiconductor device (e.g., a nonvolatile semiconductor device, such as a nonvolatile semiconductor memory, but not limited thereto), which increases the F-N current while at the same time suppressing the leakage current, at a low electric field in a gate insulating film, caused by programming. Another object of this invention is to provide a method of manufacturing such a semiconductor device. This invention therefore can provide a nonvolatile semiconductor device that has high reliability and high-speed programming capability.
Means for Solving the Problems
Representative aspects of this invention disclosed in this specification may be summarized as follows. These representative aspects are illustrative, and not limiting, of the present invention, which is defined by the appended claims.
The semiconductor device according to one aspect of the present invention has a gate electrode (e.g., floating gate electrode), on a gate insulating film on a semiconductor (e.g., silicon) substrate, that includes a first layer of amorphous silicon or polycrystalline silicon or combination (e.g., mixture, i.e., partially crystallized silicon) of amorphous and polycrystalline silicon, on (in contact with) the gate insulating film, the first layer having a thickness less than 10 nm, preferably less than 8 nm. According to another aspect of the present invention, the first layer is made of amorphous silicon, without regard to the thickness thereof.
According to the first aspect of the present invention, the thickness of the first layer, when containing polycrystalline silicon, in contact with the gate insulating film, is less than lonm, preferably less than 8nm. While not to be limiting, desirably the first layer has a minimum thickness of 1 nm, due to manufacturing considerations.
Another aspect of the present invention is a method of forming this semiconductor device. An amorphous or polycrystalline silicon film (a lower layer) of a thickness of less than 10 nm (preferably, less than 8 nm) is provided on a gate insulating film on a semiconductor substrate, and thereafter a thin insulating film (e.g., a silicon oxide film, of 0.3 to 1 nm) is provided on the amorphous or polycrystalline silicon. Then a doped polycrystalline silicon film is provided on the thin insulating film. During subsequent heat treatments (e.g., annealing, thermal oxidation, etc.) in the manufacturing process, the amorphous silicon film can be formed into a polycrystalline silicon thin film (or can remain an amorphous silicon film), and the thin insulating film can be eliminated. Moreover, during the subsequent heat treatments, impurity dopants from the doped polycrystalline silicon film can diffuse into the lower layer on the gate insulating layer, so a to make this lower layer (amorphous. silicon, polycrystalline silicon or combination thereof) conductive. In this regard, the lower layer can be formed doped or non-doped. According to another aspect of the present invention, where the lower layer on the gate insulating film remains an amorphous silicon film, the lower layer is not limited with respect to thickness.
The semiconductor device in another aspect of this invention is characterized by an electrically erasable and programmable nonvolatile semiconductor device (e.g., a memory), which includes at least a floating gate electrode and a control gate electrode, the floating gate electrode being formed over a gate insulating film and including at least an amorphous or polycrystalline silicon film with an average thickness of less than 10 nm, more preferably less than 8 nm, the control gate electrode being formed over the floating gate electrode through an interlayer insulating film so that at least a part of the control gate electrode overlaps the floating gate electrode; and a method of fabricating this semiconductor device. The advantage of this invention can be observed for the average thickness of less than 10 nm and very remarkably so for the average thickness of less than 8 nm.
The semiconductor device in still another aspect of this invention is characterized by an electrically erasable and programmable nonvolatile semiconductor device, which includes at least a floating gate electrode and a control gate electrode, the floating gate electrode being made of an amorphous silicon film formed over a gate insulating film, the control gate electrode being formed over the floating gate electrode through an interlayer insulating film so that at least a part of the control gate electrode overlaps the floating gate electrode; and a method of forming this semiconductor device.
The semiconductor device in still another aspect of this invention is characterized by an electrically erasable and programmable nonvolatile semiconductor device, which includes at least a floating gate electrode and a control gate electrode, the floating gate electrode being made of a plurality of conductor or semiconductor films formed over a gate insulating film, the control gate electrode being formed over the floating gate electrode through an interlayer insulating film so that at least a part of the control gate electrode overlaps the floating gate electrode. Of the layers forming the floating gate electrode, a layer in contact with the gate insulating film is an amorphous or polycrystalline silicon film with an average thickness of less than 10 nm, more preferably less than 8 nm. The advantage of this invention can be observed for the average thickness of less than 10 nm and very significantly so for the average thickness of less than 8 nm.
The semiconductor device in a further aspect of this invention is characterized by an electrically erasable and programmable nonvolatile semiconductor device, which includes at least a floating gate electrode and a control gate electrode, the floating gate electrode being made of a plurality of conductor or semiconductor films formed over a gate insulating film, the control gate electrode being formed over the floating gate electrode through an interlayer insulating film so that at least a part of the control gate electrode overlaps the floating gate electrode. Of the layers forming the floating gate electrode, a layer in contact with the gate insulating film is an amorphous silicon film.
The amorphous or polycrystalline silicon mentioned above means polycrystalline silicon or amorphous silicon, or a combination (e.g., mixture) of these. Based on the conventional manufacturing processes and methods in the field of semiconductor devices, polycrystalline silicon is easiest to handle.
Of the two or more layers of conductor or semiconductor material that form the floating gate electrode, layers other than the one that contacts the gate insulating film may use a material of the floating gate employed in ordinary semiconductor memory devices. For example, the semiconductor material includes silicon and the conductor material includes polycrystalline silicon, tungsten, or titanium nitride, all containing a high concentration of impurity.
In the floating gate electrode, silicon films overlying the bottom layer in contact with the gate insulating film often use polycrystalline silicon films containing phosphorus (P) or arsenic (As).
The bottom layer of the floating gate electrode in contact with the gate insulating film preferably has a thickness of less than 8 nm when it is formed of polycrystalline silicon. It is further preferred that the average grain size of the polycrystalline silicon be set lower than 20 nm. When amorphous silicon is used, the thickness is range should preferably be lower than 8 nm. The overall thickness of the floating gate electrode can be set to an ordinary thickness for a floating gate electrode of a nonvolatile semiconductor memory device.
According to various aspects of the present invention, it is desired to have amorphous silicon or small-grained polycrystalline silicon at the interface with the gate insulating film (e.g., where this silicon forms a floating gate, amorphous silicon at the interface with the tunnel insulating film); and to have, e.g., large-grained polycrystalline silicon at the interface with an interlayer insulating film, to provide a smooth surface on which the interlayer insulating film is formed. The present invention achieves this goal by at least a two-layer electrode (e.g., floating gate electrode). Where the lower layer (adjacent the gate insulating film) is of polycrystalline silicon, the lower layer is thin and is small-grained (generally, the grain size is 2xc2xd times the thickness of the layer; where the layer has a thickness of about 2 nm, the grain size would be about 5 nm); the upper layer is thick and is large-grained. Moreover in forming this electrode, a thin insulating film is provided between the lower and upper layers, so as to form the layers with different grain structure.
The semiconductor device in a further aspect of this invention is characterized by an electrically erasable and programmable nonvolatile semiconductor device, which includes at least a floating gate electrode formed over a gate insulating film and a control gate electrode formed over the floating gate electrode through an interlayer insulating film so that at least a part of the control gate electrode overlaps the floating gate electrode, wherein the floating gate electrode is made of two or more layers of conductor or semiconductor films processed by using the same mask, and wherein the thin film in contact with the gate insulating film is a silicon film with an average thickness of less than 10 nm, preferably less than 8 nm.
In this case, it is very desirable that the layer of the floating gate electrode in contact with the gate insulating film have a thickness of less than 8 nm when it is made of polycrystalline silicon. It is further preferred that the average grain size of the polycrystalline silicon be set smaller than 20 nm. When the bottom layer of the floating gate electrode in contact with the gate insulating film is made of amorphous silicon, it should very preferably have a thickness of less than 8 nm.
The thickness of the floating gate electrode as a whole can be set to an ordinary thickness. In the floating gate electrode, silicon films overlying the bottom layer in contact with the gate insulating film would generally use polycrystalline silicon films containing phosphorus (P) or arsenic (As).
The present invention has been accomplished based on the following findings on the gate insulating film.
(1) The relation between the F-N current of an MOS capacitor and the thickness of a polycrystalline silicon film as a gate electrode was examined. The study found that the F-N current significantly increases when the thickness of this polycrystalline silicon film is smaller than about 8 nm.
(2) When the gate electrode in contact with the gate insulating film is made of an amorphous silicon film, too, an effect similar to (1) was produced.
These phenomena may be explained as follows. Insulating substances such as oxygen and nitrogen present in the surface of a polycrystalline silicon film, when subjected to a high temperature heat treatment, diffuse through boundary surfaces of silicon grains to reach the rear side of the polycrystalline silicon film (i.e., on the gate insulating film side). At this time, they react with the silicon film on the rear side to form a new insulating film. This phenomenon tends to occur along the fine grain boundaries, producing a fine, rough surface on the rear side of the polycrystalline silicon film. Therefore, when an electric field is applied, the field concentrates on fine projections, which in turn is considered to cause a significant increase in the F-N current.
Further, in the above aspect of this invention, when an amorphous silicon film and other gate materials are used, there is formed at a boundary with a conductor film or semiconductor film an insulating thin film that includes an amorphous silicon film in contact with the gate insulating layer and other gate materials. This insulating thin layer is mostly a silicon oxide film, a silicon nitride film, or a combination of these. The thickness of this insulating thin film ranges between 0.3 nm and 1 nm. Of these insulating films, a thermally oxidized layer is most useful.
Amorphous silicon films formed by chemical vapor deposition are generally recognized to crystallize at temperatures higher than 600-650xc2x0 C. We have found, however, that the crystallization temperature of an amorphous silicon film became high where the amorphous silicon film has a film thickness 10 nm or less. However, this phenomenon is only observed when there is an insulating film about 0.3 nm or more on the surface of the amorphous silicon film.
FIG. 29 shows a relationship between thickness of an amorphous silicon film and a crystallization temperature thereof when the amorphous silicon film is formed by using disilane (Si2H6) at 450xc2x0 C., 30 min. in the nitrogen atmosphere.
As shown in FIG. 29, it can be understood that the crystallization temperature of an amorphous silicon film suddenly rises, when it becomes thinner than about 10 nm. For example, when the film thickness of an amorphous silicon film is 5 nm, even if it is heat treated at about 750xc2x0 C., crystallization does not occur. That is, a film thickness and a process temperature are controlled such that crystallization of the amorphous silicon film does not occur.
Accordingly, it is possible to form an optimum field effect transistor having an amorphous silicon gate electrode in case of consideration of this point of view.